May 2017

Software Engineer

ARM Ltd - Cambridge, UK

Mar. 2017
Feb. 2014

Software Engineer, PhD Student

Airbus Operations SAS - Toulouse, France
  • Designed and implemented in C a hypervisor enabling the predictable execution of safety-critical applications on MPPAs (Massively Parallel Processor Architecures) with 200+ cores.
  • Developed a scheduling tool parallelizing legacy applications on MPPAs using Directed Acyclic Graphs and makespan-optimization techniques. Implementation using Constraint Programming scaled up to 100,000 tasks.
  • Developed a case study based on a real-world avionics application to validate the approach. It exhibited cycle-accurate predictability and effective speedups close to the theoretical maximum.

Apr. 2016
Jun. 2014

Teaching Assistant

INP-ENSEEIHT - Toulouse, France
Graduate tutorials on real-time systems including:
  • scheduling algorithms (for mono- and multi-core processors);
  • timing analysis techniques;
  • synchronous programming languages.

Jul. 2013
Feb. 2013

Electronics Engineer, Intern

Airbus Operations SAS - Toulouse, France
Designed and implemented in C++ a tool assessing the conductivity requirements of the Airbus A350’s ESN (Electrical Structural Network) under complex failures modes using Graph models and Electrical Circuit Analysis.

Aug. 2012
May 2012

Research Assistant, Intern

University of Derby - School of Computing and Maths, UK
Developed a distributed real-time scheduling algorithm (inspired by the classical LLF algorithm) taking into account data locality and migration costs in Hadoop-like clusters. This involved simulation in Java with CloudSim.

Apr. 2010
Jul. 2010

Embedded Systems Engineer, Intern

Complex Systems Institute (CNRS) - Paris, France
Designed a power regulation system for a confocal microscope.


Apr. 2017

PhD in Computer Science

Institut Supérieur de l'Aéronautique et de l'Espace (ISAE) - Toulouse, France
  • Title : "Predictable Execution on Many-core Processors"
  • Advisors : Claire Pagetti & Éric Noulard (ONERA), Pascal Maurère & Benoît Triquet (Airbus)
  • Context : CIFRE (Industrial Agreement of Training through Research) Agreement Airbus / ONERA

Oct. 2013

Diplôme d'ingénieur in Electrical Engineering

Institut National des Sciences Appliquées (INSA) - Toulouse, France
Equivalent to a MSc. Major on Critical Embedded Systems.


Oct. 2016

Quentin Perret, Pascal Maurère, Éric Noulard, Claire Pagetti, Pascal Sainrat and Benoit Triquet, Mapping hard real-time applications on many-core processors, in 24th International Conference on Real-Time Networks and Systems (RTNS'16)
  • Bibtex and link
  • Abstract: Many-core processors are interesting candidates for the design of modern avionics computers. Indeed, the computation power offered by such platforms opens new horizons to design more demanding systems and to integrate more applications on a single target. However, they also bring challenging research topics because of their lack of predictability and their programming complexity. In this paper, we focus on the problem of mapping large applications on a complex platform such as the Kalray MPPA256 while maintaining a strong temporal isolation from co-running applications. We propose a constraint programming formulation of the mapping problem that enables an efficient parallelization and we demonstrate the ability of our approach to deal with large problems with a real world case study.

Apr. 2016

Quentin Perret, Pascal Maurère, Éric Noulard, Claire Pagetti, Pascal Sainrat and Benoit Triquet, Temporal isolation of hard real-time applications on many-core processors, in 22nd IEEE Real-Time Embedded Technology and Applications Symposium (RTAS'16)
  • Bibtex and link
  • Abstract: Many-core processors offer massively parallel computation power representing a good opportunity for the design of highly integrated avionics systems. Such designs must face several challenges among which 1) temporal isolation must be ensured between applications and 2) bounds of WCET must be computed for real-time safety critical applications. In order to partially address those issues, we propose an appropriate execution model, that restricts the applications behaviours, which has been implemented on the Kalray MPPA-256. We tested the correctness of the approach through a series of benchmarks and the implementation of a case study.

Jan. 2016

Quentin Perret, Pascal Maurère, Éric Noulard, Claire Pagetti, Pascal Sainrat and Benoit Triquet, Predictable composition of memory accesses on many-core processors, in Embedded Real Time Software and Systems (ERTS'16)
  • Bibtex and link
  • Abstract: The use of many-core COTS processors in safety critical embedded systems is a challenging research topic. The predictable execution of several applications on those processors is not possible without a precise analysis and mitigation of the possible sources of interference. In this paper, we identify the external DDR-SDRAM and the Network on Chip to be the main bottlenecks for both average performance and predictability in such platforms. As DDR-SDRAM memories are intrinsically stateful, the naive calculation of the Worst-Case Execution Times (WCETs) of tasks involves a significantly pessimistic upper-bounding of the memory access latencies. Moreover, the worst-case end-to-end delays of wormhole switched networks cannot be bounded without strong assumptions on the system model because of the possibility of deadlock. We provide an analysis of each potential source of interference and we give recommendations in order to build viable execution models enabling efficient composable computation of worst-case end-to-end memory access latencies compared to the naive worst-case-everywhere approach.

Mar. 2013

Quentin Perret, Gabriel Charlemagne, Stelios Sotiriadis and Nik Bessis, A deadline scheduler for jobs in distributed systems, in 27th International Conference on Advanced Information Networking and Applications Workshops (WAINA’13)
  • Bibtex and link
  • Abstract: This study presents a soft deadline scheduler for distributed systems that aims of exploring data locality management. In Hadoop, neither the Fair Scheduler nor the Capacity Scheduler takes care about deadlines defined by the user for a job. Our algorithm, named as Cloud Least Laxity First (CLLF), minimizes the extra-cost implied from tasks that are executed over a cloud setting by ordering each of which using its laxity and locality. By using our deadline scheduling algorithm, we demonstrate prosperous performance, as the number of available nodes needed in a cluster in order to meet all the deadlines is minimized while the total execution time of the job remains in acceptable levels. To achieve this, we compare the ability of our algorithm to meet deadlines with the Time Shared and the Space Shared scheduling algorithms. At last we implement our solution in the CloudSim simulation framework for producing the experimental analysis.


Apr. 2017

Best PhD award, ONERA

Information Processing and Systems (TIS) branch

Jan. 2016

Best paper award, ERTS'16 Conference

Embedded Computing Platforms category

Nov. 2012

1st Price, Xilinx national student contest

Design and implementation of a FPGA-based graphical coprocessor